Tutorials by experts will provide review presentation of relevant topics.
Invited papers will introduce the mainstream topics.
Workshops organised in correlation with the ESREF conference will give the opportunity to exchange the know-how and field returns on specific topics.
The conference will be preceded by a half-day Tutorials on Tuesday, October 6th on the following topics:
Physical Mechanisms and Modeling of the Bias Temperature Instability
by (Technische Universität Wien, Institute for Microelectronics, Austria)
Modeling efforts of negative bias temperature instability date back to the work of Jeppson and Svensson in 1977, who proposed the basic form of the popular reaction-diffusion model.
This idea is still at the heart of many modeling attempts today. Recent research indicates, however, that these models cannot capture many crucial aspects of the phenomenon. Consequently, alternative models have been developed which also consider the impact of hole trapping. This tutorial attempts to give a broad review of published modeling attempts, comparing their strengths and weaknesses.
ESD testing of devices, ICs and systems
by (NXP Semiconductors, The Netherlands)
There is a wide range of different ESD stressing methods: (vf-)TLP, HBM, MM, CDM, system level ESD ...
The key to relate results of different tests to each other is knowledge of the test conditions and device behavior. Therefore this tutorial starts with a brief overview of the different ESD standards, in which the most recent updates will be highlighted. This is followed by a discussion of suitable device characterization techniques. To predict or understand the results of any ESD test, it is essential to know how the devices behave under ESD circumstances (i.e. high currents, short duration). The work horse of ESD device characterization is the well-known Transmission Line Pulse (TLP) technique.
After an overview of the classical TLP implementations, the applications and limitations of this characterization technique will be discussed. For optimum TLP results dedicated test structures need to be available. Test structure design requirements will be explained. It will be illustrated how TLP results relate to classical component level ESD models, such as HBM and MM. It will also be shown why the relation with CDM and system level ESD is much less straightforward. Therefore it will be explored how state-of-the-art TLP extensions can help to close the gaps between the classical ESD device characterization and ESD component/system level performance.
The tutorial will conclude with a discussion on ESD requirements for products.
MEMS Reliability: Where are we now?
by (Sandia National Laboratories, USA)
MicroElectroMechanical Systems (MEMS) technology offers considerable potential due to small size, small weight, and low power of fabricated devices which can enable compelling advantages in certain product specifications. There have been significant successes in MEMS products, most notably ink-jet print heads, accelerometers, and micro-mirror projector systems. However, MEMS reliability is challenging and can be device and process dependent. This tutorial will review the current status of MEMS reliability. The reliability concerns of various devices will be discussed including accelerometers, pressure gauges, RF switches and resonators, and micro-mirror arrays. Additionally, the packaging method and environment will be discussed as part of the whole reliability program. Specifically, the effect of hydrocarbon contamination on metal switches and the subsequent increase in contact resistance over time will be reviewed. MEMS-specific solutions like wafer-level packaging and the effect on reliability will be discussed.
Thermal Management of power electronics systems
by (ECPE, Germany)
and (Semikron, Germany)
In a power electronics system many sources for thermal losses exist. They are due to on-state and switching losses of active devices, but also passive devices and busbars contribute. When the type of cooling is fixed - either natural convection, forced air cooling or liquid cooling - the thermal pathes from the heat source to the coolant can be designed. The overall goal is to keep thermal resistances as low as possible. In high-voltage systems the insulation is a necessety which has to be inserted in the thermal paths. In addidion to put several components together thermal interface materials are needed. Following the building-in reliability concept the thermal design and it's verification are demonstrated using an IGBT converter. Important data of components and materials are provided as well as concepts for intelligent testing.
Invited papers will introduce the mainstream topics.
Process dependence of BTI reliability in advanced HK MG stacks
by (CEA-LETI - France)
Bias Temperature Instabilities (BTI) reliability is investigated in advanced dielectric stacks. We show that mobility performance and NBTI reliability are strongly correlated and that they are affected by the diffusion of nitrogen species N at the Si interface. PBTI, more sensitive to bulk oxide traps, is strongly reduced in very thin dielectric films. Reducing the metal gate thickness favors the reduction of mobility degradations and NBTI, but, also strongly enhances PBTI, due to a complex set of reactions in the gate oxide. Trade off must be found to obtain a great trade off between device performance and reliability requirements.
Do ESD fails in systems correlate with IC ESD robustness?
by (Infineon Technologies - Germany)
In general, all ICs available on the market are qualified for their ESD robustness according to the well-known Human Body Model, Machine Model, and Charged Device Model. A minimum ESD robustness according to these models should guarantee safe handling in electrostatic protected areas. However, the risk of an IC being damaged by an ESD event does not vanish as soon as the IC is assembled on a printed circuit board (PCB). Boards and systems must have certain ESD robustness, too. In analogy to device level HBM, system level HBM robustness is defined in several standards, e.g. EN61000-4-2. Further stress scenarios exist of which one of the most critical stresses is the Cable Discharge Event (CDE) which endangers a wide variety of applications in the communication and automotive businesses.
As the waveforms of device and system level stress are completely different, correlation between models of both worlds are difficult to establish. Therefore, the system vendors more and more demand a specified ESD robustness for devices (ICs) according to an ESD system level standard. These requirements are based on the idea that, if all components on a board withstand a certain threshold, the board itself will withstand at least the same value. Testing ICs to a system level ESD standard requires careful considerations; first ideas are summarized in the new Standard Practice "Human Metal Model" of the ESDA/ANSI. However, the approach of deriving system ESD robustness from IC robustness is currently too much simplified and bears severe potential risks which will be discussed during the presentation.
Nevertheless, there are methodologies and approaches to use IC ESD characterization for defining ESD protection concepts for systems. Appropriate high-current characterization of ICs can be the cornerstone for a successfully optimized system ESD protection.
Laser THz emission microscope as a novel tool for LSI failure analysis
by (RIKEN, Japan)
We have proposed and developed a novel technique for noncontact inspection and localization of interconnect defects in an LSI chip using a laser terahertz emission microscope (LTEM). THz waves can be emitted from LSI chips by ultrafast transient photocurrent generated from p-n junctions excited with femtosecond (fs) laser pulses. LTEM measures THz emission images of an LSI chip by scanning it with fs laser pulses. It is possible to distinguish normal circuits from defective ones with interconnect defects by comparing their LTEM images because THz emission signals from p-n junctions strongly depend on the structure of the connected interconnects which work as THz emission antennae. Here, we report the successful results on the inspection and localization of interconnect defects such as open or short in C7552 circuit of ISCAS'85 benchmark circuits using LTEM.
Physical Analysis, Trimming and Editing of Nanoscale IC Function with Backside FIB Processing
by (Berlin University of Technology, Germany)
Physical analysis of circuit functionality, performed with IR-Beam based FA techniques, as well as conventional Circuit Edit (CE) procedures are facing severe challenges resulting from the aggressive downscaling of today's IC technology. Alternative CE- and functional chip analysis techniques are presented, all being based on backside FIB processing. Additionally, an in depth characterization of the FIB induced device performance modulation shows that a >20% speed gain can be achieved with the proposed FIB thinning procedure. In contrary to all known techniques, this offers trimming of chip internal timing conditions on fully functional samples without being bound to preplanned fuses or varactors. This paper will briefly review the necessary FIB process whereas the main focus lies on the FIB induced device modification, being discussed based on various experimental results and physical device simulations. Finally, the novel CE- and analysis techniques will be discussed regarding their fields of application, benefits compared to established techniques and theoretical limitations.
Towards Reliable Thin-Film Encapsulation of Organic Electronic Devices
by (TU Braunschweig, Germany)
Organic optoelectronic devices like organic light emitting diodes (OLEDs) and organic solar cells have emerged as very promising alternative to their established inorganic counterparts. OLEDs seed the prospect for highly efficient, low cost, large-area solutions for future ambient lighting. For these devices, an efficient encapsulation is mandatory because of the high sensitivity of many organic or electrode materials to moisture and oxygen. Reports indicate that a water vapor transmission rate (WVTR) in the range of 10-6 g/(m2 day) is needed to reach a minimum OLED lifetime of 10,000 h. As of yet, a very common technique is the encapsulation of organic devices with a glass or metal lid which is, however, not suitable for large-area, flexible or transparent applications. A promising alternative are thin-film barriers of metal-oxides or nitrides. These layers can be prepared by various techniques, e.g. sputtering or plasma enhanced chemical vapor deposition. However, typical WVTR of about 0.3 g/(m2 day), limited by imperfections in the films, render these layers inacceptable for OLED encapsulation.
Owing to its unique film forming capabilities, atomic layer deposition (ALD) could open a novel route to prepare highly efficient thin-film barrier layers directly on top of organic devices. For this purpose, low temperature ALD processes are required to minimize thermal impact on the organic functional layers with typical glass transition temperatures on the order of 100 °C. ALD permeation barriers based both on single Al2O3 layers and Al2O3/ZrO2 nano-laminates prepared at 80 °C will be presented. The quantitative assessment of permeation rates on the order of 10-6 g/(m2 day) for water and 10-3 cm3/(m2 day) for oxygen is very challenging and as of yet, no commercially available method can be applied in this range. Hence, we use a very sensitive permeation measurement technique based on the corrosion of Calcium sensors. Thereby, ultra low WVTR of about 4.7 10-5 g/(m2 day) (at 70 °C, 70 % rh) can be determined for a 130 nm thick Al2O3/ZrO2 nano-laminate. As opposed to single layers, the formation of statistical defects is found to be significantly reduced in multilayer structures. In addition, transmission electron microscopy shows that the multilayer structure also prevents the formation of extended crystallites and permeation paths for gaseous species along grain boundaries.
The functionality of the nano-laminate barriers will be verified in real OLED structures. As a prerequisite for the applicability of ALD on top of the OLEDs, it is essential to note that the ALD process leaves the device characteristics unaffected. At a starting luminance of 1000 cd/m2 an extrapolated lifetime of more than 20,000 h is achieved, comparable to that of control OLEDs sealed with a glass lid. These results support the Ca test data and underline the quality of the ALD nano-laminate barriers.
GaN HEMT Reliability
by (Massachusetts Institute of Technology, USA)
GaN HEMT technology looks increasingly attractive for a variety of high frequency and high power applications. In this technology, reliability is still a key concern. There is an increasing number of reports on studies of fundamental reliability mechanisms. As in III-V HEMTs, hot electrons appear to degrade the device, though the detailed mechanism is unclear (hot electron trapping in the SiN? Trap formation in the semiconductor?) There is now mounting evidence of the role of the inverse piezoelectric effect. The high fields that prevail under high power conditions result in strong mechanical stress in the AlGaN barrier. When the elastic energy in the AlGaN exceeds a critical value, stress is relaxed through defect formation which severely affects the device characteristics. The key signature of this mechanism is a non-reversible increase in the gate leakage current of several orders of magnitude. This degradation mechanism is voltage driven and characterized by a critical voltage below which degradation does not occur. In support of this hypothesis, recent microscopy studies have revealed very prominent crystallographic damage in the AlGaN barrier right below the gate edge where the highest electric fields are expected. An attractive feature of this hypothesis is that it suggests several paths to enhance the electrical reliability of GaN HEMTs. These strategies are yielding devices with improved reliability. This talk will review the current state of understanding of electrical reliability of GaN HEMTs, with emphasis on fundamental failure mechanisms
Reliability, Prognostics and Risk Assessment Modelling for Electronics Packaging
by (University of Greenwich, United Kingdom)
Power Electronics uses semiconductor technology to convert and control electrical power. Demands for efficient energy management, conversion and conservation, and the increasing take-up of electronics in transport systems has resulted in tremendous growth in the use of power electronics devices such as Insulated Gate Bipolar Transistors (IGBT's). The packaging of power electronics devices involves a number of challenges for the design engineer in terms of reliability. For example IGBT modules will contain a number of semiconductor dies within a small footprint bonded to substrates with aluminium wires and wide area solder joints. To a great extent, the reliability of the package will depend on the thermo-mechanical behavior of these materials. This paper details a physics of failure approach to reliability predictions of IGBT modules. It also illustrates the need for a probabilistic approach to reliability predictions that include the effects of design variations. Also discussed are technologies for predicting the remaining life of the package when subjected to qualification stresses or in service stresses using prognostics methods.
Reliability challenges of automotive power electronics
by (Semikron Elektronik GmbH & Co. KG, Germany)
A high reliability of power electronic modules is an essential requirement for hybrid traction applications. This includes a high capability to withstand the stress of repeated active and passive thermal cycles in order to meet the lifetime requirements. Active power cycling requirements are not especially severe for hybrid traction applications compared to many industrial applications. The lifetime for passive thermal cycles by a change of ambient conditions in contrast is defined by the materials and the architecture of a power module. The classical module design with Cu base plates is limited in lifetime particularly with respect to passive temperature cycles due to CTE mismatch. The advanced pressure contact design eliminates the base plate together with the base plate solder and the terminal solder interconnections and thus enhances the thermal cycling capability. As a synergy effect, this design establishes a very balanced static and transient current distribution for paralleled chips. Finally, the last remaining solder interface - the chip solder layer - can be replaced by an Ag diffusion sinter technology. The presented cycling test results will confirm, that the first 100% solder free module shows an improved performance in passive and active cycling tests.
Quasi hermetic packaging for new generation of spaceborn microwave equipment
by (Thales Alenia Space, France)
This paper presents the introduction of the quasi hermetic encapsulation of microwave hybrids for space application through different approaches evaluated at THALES ALENIA SPACE - FRANCE. Thanks to the improvement for many years of organic materials, it is now realistic to propose advanced packaging solutions like the Chip on Board approach with glob top encapsulation of active devices directly bonded on printed circuit boards. To validate this packaging approach, a very complete reliability test-plans has been proposed and performed on the different technological processes and materials in agreement with standard space quality requirements. Results will be presented and a discussion on the nature of the stresses applied during the tests will be proposed.
will be organized by Geoffroy Auvert(LETI - Grenoble - France) on Monday 5 October.
For further information, please visit: www.imec.be/efug/.
This edition will focus on a technical hot topic linked to up to date challenges in Failure Analysis.
More info on EUFANET at www.eufanet.org.